1. Technical Field
The present invention relates to a processor control device, more particularly, a processor control device in which hardware performs a polling processing.
2. Related Art
JP-A-8-83133 is an example of related art. The example discloses a technique for reducing power consumption of a central processing unit (CPU) by halting a clock signal provided to the CPU while a direct memory access (DMA) controller performs a DMA processing mode, in other words, while an I/O unit and a memory performs the DMA processing.
However, according to the hitherto known power saving technique, when a plurality of the DMAs exists and a DMA transfer is conducted, the CPU has to perform a polling processing by software and has to wait for the termination of the DMA transfer. Therefore, when the plurality of the DMAs exists and a plurality of the DMA transfers is simultaneously performed, the CPU needs to read a value in a status register, needs to determine a branch whose process is to be conducted based on the value in the status register, and needs to perform the branch process according to the value in the status register. The CPU has to repeat such operation until the DMA transfer is ended and this increases the CPU load.